1. Field of the Invention
The present invention relates to source/drain electrodes and transistor substrates for use in thin-film transistors of liquid crystal displays, semiconductor devices, and optical components. It also relates to methods for manufacturing the substrates, and display devices using the substrates. Specifically, it relates to novel source/drain electrodes including an aluminum alloy thin film as a component.
2. Description of the Related Art
Liquid crystal display devices are used in a variety of applications ranging from small-sized mobile phones to large-sized television sets with 30-inch or larger screens. They are categorized by the pixel driving method into passive-matrix liquid crystal display devices and active-matrix liquid crystal display devices. Of these, active-matrix liquid crystal display devices having thin-film transistors (hereinafter briefly referred to as TFTs) as switching devices are widely used, because they realize high-definition images and can produce images at high speed.
With reference to FIG. 1, the configuration and operating principles of a representative liquid crystal display panel for use in active-matrix liquid crystal display devices will be illustrated. A substrate with a TFT array using a hydrogenated amorphous silicon as an active semiconductor layer (hereinafter also referred to as “amorphous silicon thin-film transistor substrate”) is taken as an example. The active semiconductor layer, however, is not limited to this, and can also be a polysilicon (polycrystalline silicon) layer.
The liquid crystal display panel 100 in FIG. 1 includes a thin-film transistor substrate 1, a counter substrate 2, and a liquid crystal layer 3. The counter substrate 2 is arranged so as to face the thin-film transistor substrate 1. The liquid crystal layer 3 is arranged between the thin-film transistor substrate 1 and the counter substrate 2 and functions as an optical modulation layer. The thin-film transistor substrate 1 includes an insulative glass substrate 1a, and arranged thereon thin-film transistors 4, a transparent pixel electrode 5, and an interconnection section 6 containing scanning lines and signal lines. The transparent pixel electrode 5 is made typically from an indium tin oxide (ITO) film containing indium oxide (In2O3) and about 10 percent by mass of tin oxide (SnO2). The thin-film transistor substrate 1 is driven by a driver circuit 13 and a control circuit 14 connected thereto through a tape automated bonding (TAB) tape 12.
The counter substrate 2 includes an insulative glass substrate 1b, and a common electrode 7, a color filter 8, and a light shielding film 9. The common electrode 7 is arranged on the entire surface of the glass substrate 1b facing the thin-film transistor substrate 1. The counter substrate 2 as a whole functions as a counter electrode. The color filter 8 is arranged at such a position as to face the transparent pixel electrode 5. The light shielding film 9 is arranged at such a position as to face the thin-film transistor 4 and the interconnection section 6 on the thin-film transistor substrate 1. The counter substrate 2 further has an alignment layer 11 for aligning liquid crystal molecules (not shown) in the liquid crystal layer 3 to a predetermined direction.
The liquid crystal display panel 100 further includes polarizers 10a and 10b arranged outsides (on sides opposite to the liquid crystal layer 3) of the thin-film transistor substrate 1 and the counter substrate 2, respectively.
In the liquid crystal display panel 100, an electrical field formed between the counter electrode 2 (common electrode 7) and the transparent pixel electrode 5 controls the alignment direction of liquid crystal molecules in the liquid crystal layer 3 to thereby modulate light passing through the liquid crystal layer 3. This controls the quantity of light transmitted through the counter substrate 2 to thereby produce and display an image.
Next, the configuration and operating principles of a conventional amorphous silicon thin-film transistor substrate for use in liquid crystal display panels will be illustrated in detail with reference to FIG. 2. FIG. 2 is an enlarged view of the essential part “A” in FIG. 1.
With reference to FIG. 2, scanning lines (thin-film gate interconnections) 25 are arranged on a glass substrate (not shown). A part of the scanning lines 25 functions as a gate electrode 26 to control (to turn on and off of) the thin-film transistor. A gate insulator (silicon nitride film) 27 is arranged so as to cover the gate electrode 26. Signal lines (source/drain interconnections) 34 are arranged so as to intersect the scanning lines 25 with the gate insulator 27 interposing between them. A part of the signal lines 34 functions as a source electrode 28 of the thin-film transistor. Adjacent to the gate insulator 27 are sequentially arranged an amorphous silicon channel film (active semiconductor film) 33, signal lines (source/drain interconnections) 34, and a silicon nitride interlayer dielectric film (protecting film) 30. A liquid crystal display panel of this type is generally called as a bottom gate type panel.
The amorphous silicon channel film 33 includes a doped layer (n layer) doped with a phosphorus (P), and an intrinsic layer (i layer; also called as an undoped layer). On the gate insulator 27 is a pixel region, in which the transparent pixel electrode 5 is arranged. The transparent pixel electrode 5 is made from, for example, an ITO film containing In2O3 and SnO. A drain electrode 29 of the thin-film transistor is in contact with and electrically connected to the transparent pixel electrode 5 with the interposition of an after-mentioned barrier metal layer.
When a gate voltage is applied to the gate electrode 26 through the scanning line 25, the thin-film transistor 4 is turned on. In this state, a drive voltage which has been applied to the signal line 34 is applied from the source electrode 28 through the drain electrode 29 to the transparent pixel electrode 5. When the transparent pixel electrode 5 is applied with the drive voltage at a predetermined level, a potential difference occurs between the transparent pixel electrode 5 and the counter electrode 2, as described above with reference to FIG. 1. This potential difference orients or aligns the liquid crystal molecules in the liquid crystal layer 3, thereby bringing about light modulation.
In the thin-film transistor substrate 1, the source/drain interconnections 34 electrically connected to the source/drain electrodes; signal lines electrically connected to the transparent pixel electrode 5 (signal lines for pixel electrode); and scanning lines 25 electrically connected to the gate electrode 26 are each made from a thin film of pure alloy or an aluminum alloy such as Al—Nd (hereinafter pure aluminum and aluminum alloys are generically referred to as “aluminum alloys”). This is because such pure aluminum or aluminum alloys have a low resistivity and can be easily processed. Barrier metal layers 51, 52, 53, and 54 containing a refractory metal such as Mo, Cr, Ti, or W are arranged on and under these interconnections, as illustrated in FIG. 2.
Reasons why the conventional aluminum alloy thin films must be connected to the other components with the interposition of barrier metal layers will be described below. The aluminum alloy thin film is connected to the transparent pixel electrode 5 with the interposition of the barrier metal layers 51 and 52 as illustrated in FIG. 2. This is because, if an aluminum alloy thin film is directly connected to the transparent pixel electrode, the contact resistance between these components is high, which impairs the quality of displayed images. Aluminum used as a material for the interconnections for the transparent pixel electrode is very susceptible to oxidation, and an insulating layer of an aluminum oxide is formed at the interface between the aluminum alloy thin film and the transparent pixel electrode. The aluminum oxide is derived from oxygen formed or added during film-deposition processes of the liquid crystal display panel. The indium tin oxide (ITO) as a material for the transparent pixel electrode is an electrically conductive metal oxide, but it fails to establish an electrically Ohmic contact if the aluminum oxide layer is formed.
The deposition of such barrier metal layers, however, requires extra film-deposition chambers for the deposition thereof, in addition to sputtering systems for the deposition of the gate electrode, source electrode, and drain electrode. These extra units cause an increased production cost and a decreased productivity.
Accordingly, proposals on materials for electrodes that eliminate the necessity for barrier metal layers and enable direct contact between source/drain electrodes and a transparent pixel electrode have been made.
Japanese Unexamined Patent Application Publication (JP-A) No. Hei 11-337976 discloses a technique of using an indium zinc oxide (IZO) film containing indium oxide and about 10 percent by mass of zinc oxide as the material for the transparent pixel electrode. According to this technique, however, the ITO film that is most widely used must be replaced with the IZO film, which causes an increased material cost.
JP-A No. Hei 11-283934 discloses a method of modifying the surface of a drain electrode by subjecting the drain electrode to plasma treatment or ion implantation. The method, however, requires an extra step for the surface treatment, which causes a decreased productivity.
JP-A No. Hei 11-284195 discloses a method of constructing the gate electrode, source electrode, and drain electrode from a first layer of pure aluminum or an aluminum alloy, and a second layer of pure aluminum or an aluminum alloy further containing impurities such as nitrogen, oxygen, silicon, and carbon. This method is advantageous in that thin films for constituting the gate electrode, source electrode, and drain electrode can be continuously deposited in one film-deposition chamber. This method, however, requires an extra step of depositing the second layer containing impurities. In addition, the resulting source/drain interconnections frequently delaminate as flakes from the wall of the chamber in the step of introducing impurities into the source/drain interconnections. This is caused by a difference in thermal expansion coefficient between a film containing the impurities and a film not containing the impurities. To avoid this problem, the method requires frequent maintenance operations while stopping the film-deposition step, and this results in a significantly decreased productivity.
Under these circumstances, the present inventors have disclosed a method that eliminates the necessity for barrier metal layers, simplifies the manufacturing process without increasing the number of steps, and enables direct and reliable contact between the aluminum alloy film and the transparent pixel electrode in JP-A No. 2004-214606. The technique disclosed in JP-A No. 2004-214606 uses an aluminum alloy containing 0.1 to 6 atomic percent of at least one selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Ge, Sm, and Bi as an alloy element, and allowing at least one of these alloy elements to be a precipitated or enriched layer at the interface between the aluminum alloy film and the transparent pixel electrode to thereby achieve the object.
As is described above, the technique disclosed in JP-A No. 2004-214606 permits the direct connection between the aluminum alloy film and the transparent pixel electrode.
However, no technique has been disclosed that enables the direct contact between an amorphous silicon thin film and a source/drain interconnection containing an aluminum alloy.
As is described above, conventional interconnections as source/drain interconnections include an aluminum alloy thin film and barrier metal layers 54 and 53 arranged on and under the aluminum alloy thin film, respectively. A representative example of such an interconnection is a multilayer (three-layer) interconnection including a molybdenum (Mo) layer (lower barrier metal layer) about 50 nm thick, a pure aluminum or Al—Nd alloy thin film about 150 nm thick, and a Mo layer (upper barrier metal layer) about 50 nm thick arranged in this order. The lower barrier metal layer is arranged mainly so as to prevent interdiffusion between silicon and aluminum at the interface between the aluminum alloy thin film and the amorphous silicon thin film. The upper barrier metal layer is arranged mainly so as to prevent hillocks (nodular projections) on the surface of the aluminum alloy thin film. These mechanisms will be described in detail later.
The formation of upper and lower barrier metal layers, however, requires an extra film-deposition system for the deposition thereof, in addition to a film-deposition system for the deposition of aluminum alloy interconnections. Specifically, a film-deposition system including extra film-deposition chambers for the deposition of respective barrier metal thin films must be used. A representative example of the system is a cluster tool system including multiple film-deposition chambers connected to a transfer chamber. The system including extra units for the deposition of barrier metal layers causes an increased production cost and a reduced productivity.
In addition, the tapering of the three-layered multilayer interconnection by wet etching requires different etchants (etching solutions) for the barrier metals and for the aluminum alloy, respectively, and further requires different etching baths suitable for the etchants, to thereby cause an increased cost. An attempt has been made to carry out tapering of the multilayer interconnection using one etchant, for example, by constructing the upper barrier metal layer from pure molybdenum and the lower barrier metal layer from a molybdenum alloy. However, this technique does not realize processing with high precision.
Accordingly, strong demands have been made to provide source/drain electrodes that eliminate the need of the upper and lower barrier metal layers and permit direct connection between the amorphous silicon thin film and an aluminum alloy thin film for source/drain interconnections.
The manufacture of display devices have been conducted at lower and lower temperatures in order to improve the yield and productivity. Source/drain electrode materials for amorphous silicon thin-film transistors, for example, must have a low electrical resistivity of about 8 μΩ·cm or lower and a high thermal stability in terms of allowable temperature limit of about 350° C. The allowable temperature limit is determined according to the highest temperature applied upon the source/drain electrodes during manufacturing processes of thin-film transistor substrates. The highest temperature herein is generally the temperature at which a dielectric film as a protecting film is deposited on the electrodes. Recent advances in film-deposition technologies realize the deposition of desired dielectric films even at relatively low temperatures. In particular, they realize the deposition of such a protecting film on source/drain electrodes at about 200° C.
The source/drain electrode materials must therefore have an allowable temperature limit of around 200° C. and a sufficiently low electrical resistivity.
The above explanation has been made by taking a liquid crystal display device as a representative example, but the problems in the conventional techniques are in common in amorphous silicon thin-film transistor substrates used not only in liquid crystal display devices but also in other devices.